This invention relates to a dynamic random-access memory (DRAM).
In general, a DRAM requires a refresh. A DRAM stores information in the form of charge, but the stored charge diminishes by a leak current, etc. Thus, it is necessary to periodically amplify the charge and to thereby rewrite the information in the memory cells. This operation is referred to as refresh. Two methods of refresh are generally used, the RAS-only refresh and the CAS-before-RAS refresh. RAS and CAS respectively indicate "row address strobe" and "column address strobe".
By the RAS-only refresh method, the address of the row to be refreshed is specified, a normal input is made to a RAS input clock and a CAS input clock is aintained at the "H" level as shown by the timing chart of FIG. 2. As shown in FIG. 3, a system which uses the RAS-only refresh method is so structured that an address counter for refresh (COUNTER) 4 for specifying a refresh address is necessarily disposed outside the DRAM 7 and the part of the system necessary for the control of the DRAM 7 becomes very complicated with a read-write/refresh mode judging circuit (hereinafter simply referred to as a judging circuit) 3, a clock generator circuit (CLOCK) 2, a first address multiplexer (MUX I) 5, a second address multiplexer (MUX II) 6 and the aforementioned address counter for refresh 4. The judging circuit 3 receives from a central processing unit (CPU) 1 a signal such as an address signal and judges on the basis of this signal whether the CPU 1 is accessing the DRAM 7 or not. This judging circuit 3 is also adapted to control the first address multiplexer 5, selecting the address received from the CPU 1 if the CPU 1 is found to be accessing the DRAM 7 and the address of the address counter for refresh 4 in other cases. It also controls the increment of the address counter for refresh 4, etc.
The clock generator circuit 2 is for generating clock signals such as the control signals RAS, CAS, etc. for the DRAM 7. The second address multiplexer 6 is used when row and column addresses are inputted by time division.
By the CAS-before-RAS refresh method, on the other hand, the address of the row to be refreshed need not be specified from outside but its timing must be inputted as shown in FIG. 4 at the time of the refresh. By this method, there is no need for an outside address counter because the address counter for refresh is contained within the DRAM 7. A system using the CAS-before-RAS refresh method is shown in FIG. 5. It can be seen that the outside system is simpler than that shown in FIG. 3 because the address counter for refresh 17 and the first address ultiplexer 18 in this case are contained within the DRAM -5. When the CPU 11 is not accessing the DRAM I5, however, the timing of the CAS-beforeRAS shown in FIG. 4 must be provided from outside and the clock generator circuit 12 becomes structurally more complicated correspondingly. Moreover, a judging circuit 13 is required outside the DRAM 15, and another judging circuit 16 is required also inside the DRAM 15 for identifying the mode of operation when the timing shown in FIG. 4 is inputted. The second address multiplexer 14, as explained above by way of FIG. 3, is also for use when row and column addresses are inputted by time division.